Conventional Phase Locked Loop (PLL) circuits that are used as phase synchronous circuits and oscillator circuits in transmission devices and server devices receive input of a reference signal with a reference frequency and generate an output signal with a desired frequency that is synchronized or multiplied based on the reference signal.
FIG. 10 is a block diagram of a schematic configuration of the interior of a conventional PLL circuit.
A PLL circuit 100 illustrated in FIG. 10 includes a 1/N frequency divider 101 that divides the frequency of a referenced signal, which is an output signal of the PLL circuit 100 as described below, by N; a phase frequency comparator 102; a charge pump 103; a low-pass filter 104; and a voltage controlled oscillator (hereinafter, described as a “VCO (Voltage Controlled Oscillator)”) 105.
The PLL circuit 100 outputs a referenced signal with a desired frequency that is synchronized with a reference signal, on the basis of a phase difference signal.
The phase frequency comparator 102 compares frequencies and phases between the referenced signal whose frequency has been divided by N by the 1/N frequency divider 101 and the reference signal, and outputs a phase difference signal to the charge pump 103 as a result of the comparison. The phase difference signal includes an up signal that is output when the phase of the referenced signal is delayed from the phase of the reference signal, and a down signal that is output when the phase of the referenced signal is advanced from the phase of the reference signal.
When the referenced signal is synchronized with the reference signal, the phase frequency comparator 102 outputs both of the up signal and the down signal to the charge pump 103 in order to prevent the charge pump 103 from becoming a dead zone and unstable.
The charge pump 103 outputs a current pulse to the low-pass filter 104 on the basis of the phase difference signal output by the phase frequency comparator 102. Specifically, the charge pump 103 includes a P-channel transistor (hereinafter, described as a “P channel”) and an N-channel transistor (hereinafter, described as an “N channel”). When detecting the up signal, the charge pump 103 outputs a current pulse for flowing out an electric current via the P-channel to the low-pass filter 104, and, when detecting the down signal, the charge pump 103 outputs a current pulse for drawing an electric current via the N channel to the low-pass filter 104.
The low-pass filter 104 outputs a control voltage to the VCO 105 in accordance with the current pulse.
The VCO 105 generates and outputs a referenced signal with a desired frequency in accordance with the control voltage.
It is known that the control voltage used for generating the desired frequency changes with a process variation that occurs due to manufacturing (process) conditions or the like. Examples of the process variation include a variation in device properties of the P channel, the N channel, and the like due to manufacturing conditions or manufacturing environment and a variation due to reduction in a power-supply voltage and the short channel effect in a MOS process.
Therefore, a technology related to a PLL circuit as explained below has been disclosed in order to stabilize the control voltage at the desired frequency. FIG. 11 is a block diagram of a schematic configuration of the interior of a conventional PLL circuit for stabilizing a control voltage. In a PLL circuit 200 illustrated in FIG. 11, a frequency counter 201 monitors a frequency of a reference signal. Furthermore, in the PLL circuit 200, a control unit 202 reads, from a memory 203, a current value corresponding to the frequency of the reference signal that is obtained as a result of the monitoring, and sets the read current value simultaneously to the P channel and the N channel of the charge pump 103 to correct current values.
Patent Literature 1: Japanese Laid-open Patent Publication No. 2008-034926
However, in the conventional PLL circuit, if a process variation occurs, the current value of each of the P channel and the N channel may be deviated from a design value that is a target value (hereinafter, described as a “target design value”) even when a referenced signal is synchronized with a reference signal. When a deviation from the target design value occurs, noise or jitter occurs in the control voltage, which is a problem. The jitter indicates a deviation or a variation of the referenced signal over time.
The above problem will be explained below with reference to FIG. 12 and FIG. 13.
FIG. 12A is a diagram illustrating oscillation frequency-control voltage characteristics of the VCO 105. FIG. 12B is a diagram illustrating current-control voltage characteristics of the charge pump 103.
FIG. 12A indicates that the characteristics of the control voltage (the X coordinate) versus the oscillation frequency (the Y coordinate) vary with a process variation. As illustrated in FIG. 12A, control voltages (V1, V2, V3) used to obtain a desired oscillation frequency become different from one another due to variations among three types of processes (a1, a2, a3). Here, it is assumed that a2 represents a typical process condition at the time of design.
FIG. 12B indicates that current values of respective electric currents output from the N channel and the P channel of the charge pump 103 are deviated from each other when the control voltage varies. At the control voltage V2 under the typical process condition a2, a current value Ip of the P channel and a current value In of the N channel match each other at the target design value.
However, if the control voltage decreases because of the process condition a1, the current value Ip of the P channel becomes greater than the target design value and the current value In of the N channel becomes smaller than the target design value. This is because the decrease in the control voltage causes a source-drain voltage to decrease to thereby decrease the current value due to the property of the N channel, and causes a source-drain voltage to increase to thereby increase the current value due to the property of the P channel.
A problem that occurs when the current values of the respective electric currents output from the P channel and the N channel are deviated from each other as described above will be explained below with reference to FIG. 13. It is assumed that a referenced signal is synchronized with a reference signal. FIG. 13(a) is a diagram illustrating a case that respective output currents output from the N channel and the P channel of the charge pump 103 are deviated from each other. FIG. 13(b) is a diagram illustrating an influence on the control voltage. FIG. 13(c) is a diagram illustrating an influence on the reference signal and the referenced signal.
In FIG. 13(a), when the current value Ip of the P channel of the charge pump 103 is greater than the current value In of the N channel, a pulse width wp of the electric current of the P channel is narrower than a pulse width wn of the electric current of the N channel. This is because the low-pass filter 104 sets the pulse widths in accordance with the current values so that the same results can be obtained through integration based on the respective current pulses output from the P channel and the N channel. A1 indicates a current pulse that is obtained when the current value Ip of the P channel and the current value In of the N channel match each other, that is, when, for example, the typical process condition a2 is employed.
FIG. 13(b) illustrates the control voltage at the current pulse illustrated in FIG. 13(a). Because the pulse widths and the current values of respective electric currents output from the N channel and the P channel are different from each other, the control voltage becomes unstable.
FIG. 13(c) illustrates respective phases of the reference signal and the referenced signal at the current pulse illustrated in FIG. 13(a). The current pulse of the P channel rises at the same time when the reference signal rises, so that a stationary phase difference (wn−wp) occurs between the reference signal and the referenced signal.
Therefore, if only one of the current pulses of the P channel and the N channel rises at a timing at which the one of the current pulses of the P channel and the N channel rises, or if amplitudes of current pulses vary even when both of the current pulses rise, the electric currents are not cancelled out, resulting in noise in the control voltage.
Furthermore, the PLL circuit causes a delay time by the stationary phase difference between the reference signal and the referenced signal, so that jitter occurs.
Moreover, the conventional PLL circuit 200 sets a current value simultaneously to the P channel and the N channel to correct current values. Therefore, even when an electric current output from the charge pump 103 is made to pass through a high-load resistance, the current values of respective electric currents output from the P channel and the N channel are deviated from a target design value due to reduction in a power-supply voltage and due to the short channel effect in a MOS process. Therefore, the stationary phase difference occurs by a difference between the current pulse widths, resulting in jitter.